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19-3874; Rev 1; 2/06
Low-Cost, SMBus, CCFL Backlight Controller
General Description
The MAX8759 integrated cold-cathode fluorescent lamp (CCFL) inverter controller is designed to drive CCFLs using a full-bridge resonant inverter. The resonant operation ensures reliable striking and provides near-sinusoidal waveforms over the entire input range. The controller operates over a wide input-voltage range of 4.5V to 28V with high power to light efficiency. The device also includes safety features that effectively protect against single-point fault conditions such as lamp-out, secondary overvoltage, and secondary short-circuit faults. The MAX8759 provides accurate lamp-current regulation (2.5%) for superior CCFL inverter performance. The lamp current is adjustable with an external resistor; 10:1 dimming range can be achieved by turning the CCFL on and off using a digital pulse-width modulation (DPWM) method, while maintaining the lamp-current constant. The MAX8759 provides three mechanisms for controlling brightness: 2-wire SMBusTM-compatible interface, external ambient-light sensor (ALS), or system PWM control. The MAX8759 supports Intel display power-saving technology (DPST) to maximize battery life. The device includes two lamp-current feedback input pins that support dual-lamp applications with a minimum number of external components. The MAX8759 controls a full-bridge inverter for maximum efficiency and directly drives four external n-channel power MOSFETs. An internal 5.35V linear regulator powers the MOSFET drivers and most of the internal circuitry. The MAX8759 is available in a space-saving, 28-pin, thin QFN package and operates over a -40C to +85C temperature range.
Features
Accurate Dimming Control Using SMBus, PWM Interface, or Ambient Light Sensor 10:1 Dimming Range with 256-Step Resolution Resonant-Mode Operation Longer Lamp Life with Near Sinusoidal LampCurrent Waveform Guaranteed Striking Capability High-Power-to-Light Efficiency Wide Input-Voltage Range (4.5V to 28V) Input Feed-Forward for Excellent Line Rejection 2.5% Lamp-Current Regulation Adjustable 1.5% Accurate DPWM Frequency Dual Lamp-Current Feedback Inputs Comprehensive Fault Protection Secondary Voltage Limiting Primary Current Limit with Lossless Sensing Lamp-Out Protection with Adjustable Timeout Secondary Short-Circuit Protection Small 28-Pin, 5mm x 5mm, Thin QFN Package
MAX8759
Minimal Operating Circuit
Applications
Notebooks LCD Monitors Automotive Infotainment
MAX8759
Ordering Information
PART MAX8759ETI+ TEMP RANGE -40C to +85C PINPACKAGE 28 Thin QFN-EP* 5mm x 5mm PKG CODE T2855-6
+ Denotes lead-free package. *EP = Exposed pad. Pin Configuration appears at end of data sheet. SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Cost, SMBus, CCFL Backlight Controller MAX8759
ABSOLUTE MAXIMUM RATINGS
BATT to GND..........................................................-0.3V to +30V BST1, BST2 to GND ...............................................-0.3V to +36V BST1 to LX1, BST2 to LX2 ........................................-0.3V to +6V FREQ, VCC, VDD to GND .........................................-0.3V to +6V SDA, SCL to GND.....................................................-0.3V to +6V ALS, COMP, PWMI, PWMO, TFLT, DEL, VALS to GND .......................-0.3V to (VCC + 0.3V) GH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) GH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) GL1, GL2 to GND .......................................-0.3V to (VDD + 0.3V) IFB1, IFB2, ISEC, VFB to GND ....................................-3V to +6V PGND1, PGND2 to GND .......................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN 5mm x 5mm (derate 21.3mW/C above +70C) .............................1702mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VBATT = 12V, VCC = VDD, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER BATT Input Voltage Range BATT Quiescent Current BATT Quiescent Current, Shutdown VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis VCC POR Threshold VCC POR Hysteresis GH1, GH2, GL1, GL2 On-Resistance, Low State GH1, GH2, GL1, GL2 On-Resistance, High State BST1, BST2 Leakage Current Resonant Frequency Range Minimum On-Time Maximum Off-Time Current-Limit Threshold Zero-Current-Crossing Threshold Current-Limit Leading-Edge Blanking IFB1, IFB2 Input-Voltage Range IFB1 Regulation Point IFB2 Regulation Point -3 765 780 785 800 LX1 - PGND1, LX2 - PGND2 LX1 - PGND1, LX2 - PGND2 ITEST = 100mA, VCC = VDD = 5V ITEST = 100mA, VCC = VDD = 5V VBST_ = 12V, VLX_ = 7V Guaranteed by design 30 350 40 415 3 500 60 430 8 350 +3 805 820 Rising edge CONDITIONS VCC = VDD = VBATT VCC = VDD = open MAX8759 is enabled MAX8759 is disabled MAX8759 is enabled, 6V < VBATT < 28V, 0 < ILOAD < 10mA MAX8759 is disabled, no load VCC rising (leaving lockout) VCC falling (entering lockout) 3.7 230 1.75 50 3 10 4 6 18 10 80 700 80 445 13 5.2 3.5 VBATT = 28V VBATT = VCC = 5V 0.1 5.35 4.3 MIN 4.5 5.5 2.5 TYP MAX 5.5 28.0 5 5 2 5.5 5.5 4.3 UNITS V mA A V V V mV V mV A kHz ns s mV mV ns V mV mV
2
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Low-Cost, SMBus, CCFL Backlight Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VBATT = 12V, VCC = VDD, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER IFB1, IFB2 Input Bias Current IFB1, IFB2 Lamp-Out Threshold IFB1, IFB2 to COMP Transconductance COMP Output Impedance COMP Discharge Current During Overvoltage or Overcurrent Fault COMP Discharge Current During DPWM Off-Time DPWM Rising-to-Falling Ratio ISEC Input Voltage Range ISEC Overcurrent Threshold ISEC Input Bias Current VFB Input Voltage Range VFB Input Impedance VFB Overvoltage Threshold VFB Undervoltage Threshold VFB Undervoltage Delay RFREQ = 169k RFREQ = 169k, TA = +25C to +85C DPWM Oscillator Frequency RFREQ = 169k RFREQ = 340k RFREQ = 100k PWMO Output Impedance PWMI Input Low Voltage PWMI Input High Voltage PWMI Input Hysteresis PWMI Input Bias Current PWMI Input Frequency Range PWMI Full-Range Accuracy PWMI duty cycle = 100% PWMI Brightness Setting ALS Full-Adjustment Range ALS Full-Range Accuracy ALS Input Bias Current VALS Output Voltage VALS Leakage Current VALS On-Resistance MAX8759 is enabled, 6V < VBATT < 28V, ILOAD = 1mA MAX8759 is disabled, VALS = GND MAX8759 is enabled -0.1 5.10 -3 30 5.30 PWMI duty cycle = 50% PWMI duty cycle = 0% 98 48 9.7 0 100 50 10.0 52 10.3 1.8 5 +0.1 5.50 +3 60 V LSB A V A % -0.3 5 2.1 300 +0.3 50 5 20 207 205 VISEC = 1.25V VVFB = 2.6V or VISEC = 1.5V VCOMP = 1.5V VIFB1,2 = 0 -3 1.18 -0.3 -4 150 2.2 210 300 2.3 240 250 210 210 106 343 40 60 0.7 k V V mV A kHz LSB 213 215 Hz 1.21 0.5V < VCOMP < 4V CONDITIONS 0 < VIFB1,2 < 3V -3V < VIFB1,2 < 0 MIN -3 -230 575 60 6 500 90 600 100 12 1000 110 2.5 +3 1.26 +0.3 +4 450 2.4 280 V V A V M V mV s 625 160 24 2000 130 TYP MAX +3 UNITS A mV S M A A
MAX8759
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VBATT = 12V, VCC = VDD, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Zero-Crossing Delay Maximum Zero-Crossing Delay DEL Disable Threshold CONDITIONS VBATT = 9V, RTHR = 120k VBATT = 12V, RTHR = 120k VBATT = 18V, RTHR = 120k DEL rising DEL falling VISEC < 1.25V and VIFB < 540mV; VFLT = 2V TFLT Charge Current TFLT Trip Threshold SDA, SCL, Input Low Voltage SDA, SCL, Input High Voltage SDA, SCL, Input Hysteresis SDA, SCL, Input Bias Current SDA Output Low Sink Current SMBus Frequency SMBus Free Time SCL Serial Clock High Period SCL Serial Clock Low Period START Condition Setup Time START Condition Hold Time STOP Condition Setup Time from SCL SDA Valid to SCL Rising-Edge Setup Time, Slave Clocking in Data SCL Falling Edge to SDA Transition SCL Falling Edge to SDA Valid, Reading Out Data tBUF tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tDV VSDA = 0.4V -1 4 10 4.7 4 4.7 4.7 4 4 250 0 200 1 100 2.1 100 +1 VISEC < 1.25V and VIFB > 660mV; VFLT = 2V VISEC > 1.25V and VIFB > 660mV; VFLT = 2V Rising edge 3.8 0.9 -1.5 115 3.7 1.0 -1.2 135 4 1.1 -0.8 155 4.3 0.7 V V V mV A mA kHz s s s s s s ns ns ns A MIN 0 1.50 3.2 TYP 0.15 1.80 3.8 MAX 0.30 2.10 4.4 4.5 UNITS s s V
4
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Low-Cost, SMBus, CCFL Backlight Controller
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VBATT = 12V, VCC = VDD, TA = -40C to +85C.) (Note 1)
PARAMETER BATT Input Voltage Range BATT Quiescent Current VCC Output Voltage, Normal Operation VCC Output Voltage, Shutdown VCC Undervoltage Lockout Threshold GH1, GH2, GL1, GL2 On-Resistance, Low State GH1, GH2, GL1, GL2 On-Resistance, High State Resonant Frequency Range Minimum On-Time Maximum Off-Time Current-Limit Threshold Zero-Current Crossing Threshold IFB1, IFB2 Input Voltage Range IFB1 Regulation Point IFB2 Regulation Point IFB1, IFB2 Input Bias Current IFB1, IFB2 Lamp-Out Threshold IFB1, IFB2 to COMP Transconductance COMP Output Impedance COMP Discharge Current During Overvoltage or Overcurrent Fault COMP Discharge Current During DPWM Off-Time ISEC Input Voltage Range ISEC Overcurrent Threshold VFB Input Voltage Range VFB Input Impedance VFB Overvoltage Threshold VFB Undervoltage Threshold DPWM Oscillator Frequency PWMO Output Impedance RFREQ = 169k VVFB = 2.6V or VISEC = 1.5V VCOMP = 1.5V 0.5V < VCOMP < 4V -3V < VIFB1,2 < 0 LX1 - PGND1, LX2 - PGND2 LX1 - PGND1, LX2 - PGND2 CONDITIONS VCC = VDD = VBATT VCC = VDD = open MAX8759 is enabled VBATT = 28V VBATT = VCC = 5V 5.2 3.5 3.7 6 18 30 350 40 410 3 -3 760 775 -230 565 60 6 500 90 -3 1.18 -4 150 2.2 210 203 20 635 160 25 2000 130 +3 1.26 +4 450 2.4 280 217 60 80 700 80 450 13 +3 810 825 MIN 4.5 5.5 TYP MAX 5.5 28.0 5 5 5.5 5.5 4.3 UNITS V mA V V V kHz ns s mV mV V mV mV A mV S M A A V V V M V mV Hz k
MAX8759
MAX8759 is enabled, 6V < VBATT < 28V, 0 < ILOAD < 10mA MAX8759 is disabled, no load VCC rising (leaving lockout) VCC falling (entering lockout) ITEST = 100mA, VCC = VDD = 5V ITEST = 100mA, VCC = VDD = 5V Guaranteed by design
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VBATT = 12V, VCC = VDD, TA = -40C to +85C.) (Note 1)
PARAMETER PWMI Input Low Voltage PWMI Input High Voltage PWMI Input Frequency Range PWMI duty cycle = 100% PWMI Brightness Setting ALS Full-Adjustment Range VALS Output Voltage VALS On-Resistance Zero-Crossing Delay Maximum Zero-Crossing Delay DEL Disable Threshold MAX8759 is enabled, 6V < VBATT < 28V, ILOAD = 1mA MAX8759 is enabled VBATT = 9V, RTHR = 100k VBATT = 12V, RTHR = 100k VBATT = 16V, RTHR = 100k DEL rising DEL falling VISEC < 1.25V and VIFB < 540mV; VFLT = 2V TFLT Charge Current TFLT Trip Threshold SDA, SCL, Input Low Voltage SDA, SCL, Input High Voltage SDA Output Low-Sink Current SMBus Frequency SMBus Free Time SCL Serial Clock High Period SCL Serial Clock Low Period START Condition Setup Time START Condition Hold Time STOP Condition Setup Time from SCL SDA Valid to SCL Rising-Edge Setup Time, Slave Clocking in Data SCL Falling Edge to SDA Transition SCL Falling Edge to SDA Valid, Reading Out Data tBUF tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tDV VSDA = 0.4V 2.1 4 10 4.7 4 4.7 4.7 4 4 250 0 200 100 VISEC < 1.25V and VIFB > 660mV; VFLT = 2V VISEC > 1.25V and VIFB > 660mV; VFLT = 2V Rising edge 3.9 0.8 -1.5 115 3.7 1.2 -0.8 155 4.3 0.7 V V V mA kHz s s s s s s ns ns ns A 0 1.50 3.2 PWMI duty cycle = 50% PWMI duty cycle = 0% 2.1 5 98 48 9.7 0 5.10 52 10.3 1.8 5.50 60 0.3 2.10 4.4 4.5 V V s s V % 50 CONDITIONS MIN TYP MAX 0.7 UNITS V V kHz
Note 1: Specifications to -40C are guaranteed by design, not production tested.
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Low-Cost, SMBus, CCFL Backlight Controller
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
HIGH-INPUT VOLTAGE OPERATION (VIN = 20.0V) LINE TRANSIENT RESPONSE (8V TO 20V)
MAX8759 toc03
MAX8759
LOW-INPUT VOLTAGE OPERATION (VIN = 8.0V)
MAX8759 toc01
MAX8759 toc02
A
A
A
B
B
B
C
C
C
D 10s/div A: VFB, 2V/div B: LX1, 10V/div C: LX2, 10V/div D:IFB, 2V/div A: VFB, 2V/div B: LX1, 20V/div 10s/div C: LX2, 20V/div D: IFB, 2V/div
D 100s/div A: VIN, 10V/div B: COMP, 2V/div C: IFB, 2V/div D: LX1, 20V/div
D
LINE TRANSIENT RESPONSE (20V TO 8V)
MAX8759 toc04
MINIMUM BRIGHTNESS STARTUP WAVEFORM (SMBus MODE, BRIGHTNESS REGISTER = 0x00)
MAX8759 toc05
MINIMUM BRIGHTNESS DPWM OPERATION (SMBus MODE, BRIGHTNESS REGISTER = 0x00)
MAX8759 toc06
A A A B B C B C C D 100s/div A: VIN, 10V/div B: COMP, 2V/div C: IFB, 2V/div D: LX1, 20V/div A: VFB, 2V/div B: COMP, 1V/div 2ms/div C: IFB, 2V/div A: VFB, 2V/div B: COMP, 1V/div 2ms/div C: IFB, 2V/div
50% BRIGHTNESS DPWM OPERATION (SMBus MODE, BRIGHTNESS REGISTER = 0x80)
MAX8759 toc07
DPWM SOFT-START
MAX8759 toc08
DPWM SOFT-STOP
MAX8759 toc09
A
A A B
B B C C C
2ms/div A: VFB, 2V/div B: COMP, 1V/div C: IFB, 2V/div A: VFB, 2V/div B: COMP, 1V/div
40s/div C: IFB, 2V/div A: VFB, 2V/div B: COMP, 1V/div
40s/div C: IFB, 2V/div
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
OPEN-LAMP VOLTAGE LIMITING AND TIMEOUT
MAX8759 toc010
SECONDARY SHORT-CIRCUIT PROTECTION AND TIMEOUT
MAX8759 toc011
SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX8759 toc12
80 SWITCHING FREQUENCY (kHz)
A
A
70
60
B
B
50
C
C
40
30 200ms/div A: VFB, 2V/div B: COMP, 500mV/div C: TFLT, 5V/div A: ISEC, 2V/div B: COMP, 1V/div 2ms/div C: TFLT, 1V/div 5 10 15 VIN (V) 20 25
DPWM FREQUENCY vs. RFREQ
MAX8759 toc13
RMS LAMP CURRENT vs. INPUT VOLTAGE
ILAMP = 7mA RMS LAMP CURRENT (mA) 7 ILAMP = 6mA 6 ILAMP = 5mA 5 ILAMP = 4mA 4
MAX8759 toc14
RMS LAMP CURRENT (ILAMP = 6mA) vs. INPUT VOLTAGE
MAX8759 toc15
350 300 DPWM FREQUENCY (Hz) 250 200 150 100 50 50 100 150 200 RFREQ (k) 250 300
8
6.2 6.1 RMS LAMP CURRENT (mA) 6.0 5.9 5.8 5.7 5.6
3 350 5 10 15 INPUT VOLTAGE (V) 20 25
5
10
15 INPUT VOLTAGE (V)
20
25
NORMALIZED BRIGHTNESS vs. SMBus BRIGHTNESS SETTING
MAX8759 toc16
NORMALIZED BRIGHTNESS vs. PWMI DUTY CYCLE
MAX8759 toc17
NORMALIZED BRIGHTNESS vs. ALS VOLTAGE
MAX8759 toc18
100 NORMALIZED BRIGHTNESS (%)
100 NORMALIZED BRIGHTNESS (%)
100 NORMALIZED BRIGHTNESS (%)
80
80
80
60
60
60
40
40
40
20
20
20
0 0 20 40 60 80 100 BRIGHTNESS SETTING (%)
0 0 0.2 0.4 0.6 0.8 1.0 PWMI DUTY RATIO
0 0 0.4 0.8 1.2 1.6 2.0 VALS (V)
8
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Low-Cost, SMBus, CCFL Backlight Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD, TA = +25C, unless otherwise noted.)
NORMALIZED BRIGHTNESS vs. SMBus BRIGHTNESS AND PWMI DUTY CYCLE
MAX8759 toc19
MAX8759
NORMALIZED BRIGHTNESS vs. ALS VOLTAGE AND PWMI DUTY CYCLE
MAX8759 toc20
100 NORMALIZED BRIGHTNESS (%)
1.0
80
SMB = 0xFF
0.8 VALS = 1.8V VALS = 1.8V
60
0.6
40
0.4
20
SMB = 0x80
0.2
VALS = 0.8V
0 0 0.2 0.4 0.6 0.8 1.0 PWMI DUTY RATIO
0 0 0.2 0.4 0.6 0.8 1.0 PWMI DUTY RATIO
ALS TRANSIENT RESPONSE (ALSDEL1 = ALSDEL0 = 0)
MAX8759 toc21
VCC LINE REGULATION
MAX8759 toc22
5.35
5.34 VCC VOLTAGE (V) A
5.33
5.32
B
5.31
5.30 1s/div A: ALS, 1V/div B: COMP, 1V/div 8 12 16 INPUT VOLTAGE (V) 20 24
VCC LOAD REGULATION
MAX8759 toc23
VCC VOLTAGE vs. TEMPERATURE
MAX8759 toc24
5.35 VIN = 24V
5.32
5.34 VCC VOLTAGE (V)
5.31 VCC VOLTAGE (V)
5.33
5.30
5.32 VIN = 12V
5.29
5.31
5.28
5.30 0 2 4 6 8 10 12 LOAD CURRENT (mA)
5.27 -40 -20 0 20 40 60 80 TEMPERATURE (C)
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 NAME BATT SDA SCL TFLT VALS ALS PWMI PWMO FREQ COMP DEL FUNCTION Supply Input. BATT is the input to the internal 5.35V linear regulator that powers the device. Bypass BATT to GND with a 0.1F ceramic capacitor. SMBus Serial Data Input SMBus Serial Clock Input Fault-Timer Adjustment Pin. Connect a capacitor from TFLT to GND to set the time-out periods for openlamp and secondary overcurrent faults. Ambient-Light-Sensor Supply Pin. Bypass VALS to GND with a 0.1F capacitor. Ambient-Light-Sensor Input DPST Control Input DPST Buffer Output. Connect a capacitor between PWMO and GND. The capacitor forms a lowpass filter with an internal 40k (typ) resistor for filtering the DPST signal. Chopping-Frequency Adjustment Pin. Connect a resistor from FREQ to GND to set the DPWM frequency: fDPWM = 210Hz x 169k / RFREQ. Transconductance Error Amplifier Output. A compensation capacitor connected between COMP and GND sets the rise and fall time of the lamp-current envelope in DPWM operation. Adaptive Zero-Crossing-Delay Adjustment Pin. Connect a resistor between DEL and GND to adjust the range of the zero-crossing delay. Connecting DEL to VCC disables the zero-crossing delay function. Lamp-Current-Feedback Input. The IFB1 sense signal is internally full-wave rectified. IFB1 is compared with IFB2 and the larger is used for lamp-current regulation. The average value of the rectified signal is regulated to 785mV (typ) by controlling the on-time of high-side switch. An open-lamp fault is generated if the peak voltage of IFB1 is below 600mV for a fault delay period set by TFLT. Lamp-Current-Feedback Input. The IFB2 sense signal is internally full-wave rectified. IFB1 is compared with IFB2 and the larger is used for lamp-current regulation. The average value of the rectified signal is regulated to 800mV (typ) by controlling the on-time of high-side switch. An open-lamp fault is generated if the peak voltage of IFB2 is below 600mV for a fault-delay period set by TFLT. IFB2 input can be disabled by connecting IFB2 to VCC. Transformer Secondary Voltage-Feedback Input. A capacitive voltage-divider between the high-voltage terminal of the CCFL tube and GND sets the maximum average lamp voltage during striking and lamp-out fault. When the peak voltage on VFB exceeds the internal overvoltage threshold, the controller turns on an internal current sink, discharging the COMP capacitor to limit the switch on-time. The VFB pin is also used to detect a secondary undervoltage condition. If the peak voltage on VFB is below 230mV continuously for 250s during the DPWM ON period, the MAX8759 shuts down. Transformer Secondary Current-Feedback Input. A current-sense resistor connected between the lowvoltage end of the transformer secondary and the ground sets the maximum secondary current during short-circuit fault. When the peak voltage on ISEC exceeds the internal overcurrent threshold, the controller turns on an internal current sink discharging the COMP capacitor. GH1 Gate-Driver Return. LX1 is the input to the current-limit and zero-crossing comparators. The device senses the voltage across the low-side MOSFET NL1 to detect primary current zero crossing and primary overcurrent. High-Side MOSFET NH1 Gate Driver Output
12
IFB1
13
IFB2
14
VFB
15
ISEC
16 17
LX1 GH1
10
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Low-Cost, SMBus, CCFL Backlight Controller
Pin Description (continued)
PIN 18 19 20 21 22 23 24 25 26 NAME BST1 PGND1 GL1 VDD GL2 PGND2 BST2 GH2 LX2 FUNCTION GH1 Gate-Driver Supply Input. Connect a 0.1F capacitor from LX1 to BST1. Power Ground. PGND1 is the return for the GL1 gate driver. Low-Side MOSFET NL1 Gate Driver Output Low-Side Gate-Driver Supply Input. Connect VDD to the output of the internal linear regulator (VCC). Low-Side MOSFET NL2 Gate-Driver Output Power Ground. PGND2 is the return for the GL2 gate driver. GH2 Gate-Driver Supply Input. Connect a 0.1F capacitor from LX2 to BST2. High-Side MOSFET NH2 Gate-Driver Output GH2 Gate-Driver Return. LX2 is the input to the current-limit and zero-crossing comparators. The device senses the voltage across the low-side MOSFET NL2 to detect primary current zero crossing and primary overcurrent. Analog Ground. The ground return for VCC, REF, and other analog circuitry. Connect GND to PGND under the IC at the IC's backside exposed metal pad. 5.35V/10mA Internal Linear-Regulator Output. VCC is the supply voltage for the device. Bypass VCC with a 0.47F ceramic capacitor to GND. Exposed Backside Pad. Connect PAD to GND.
MAX8759
27 28 --
GND VCC EP
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11
Low-Cost, SMBus, CCFL Backlight Controller MAX8759
INPUT VOLTAGE 7.5V TO 24V
F1 2A 21 C7 0.1F 21 C8 0.47F GND BST2 DEL BST1 VCC C9 0.47F 28 VCC GH1 24 18 17 C10 0.1F 2 FDC6561AN C2 2.2F C1 10F 25V
BATT
VDD
27
11
N1A
N1B C3 2.2F
SMB_DATA
MAX8759
SDA
LX1
16 C11 0.1F
SMB_CLOCK
LX2 3 SCL GL1 7 PWMI PGND1 PWMO PGND2 GL2 9 R3 169k 1% FREQ
26
20
PWM INPUT
N2A
N2B T1 1:110 C4 10pF 3kV CCFL
19
FDC6561AN
8 C12 1F
23 22
GH2
25
IFB1
12
ALS SUPPLY C15 0.1F
IFB2 5 VALS VFB
13
VCC
14
ISEC ALS OUTPUT 6 ALS
15 C6 68nF C13 6.8nF C14 0.22F R2 3.9k C5 10nF
R1 150 1%
COMP
10
TFLT
4
Figure 1. Typical MAX8759 Single-Lamp Operating Circuit 12 ______________________________________________________________________________________
Low-Cost, SMBus, CCFL Backlight Controller
Typical Operating Circuit
The MAX8759 typical operating circuit (Figure 1) is a single-lamp CCFL backlight inverter for notebook computer TFT LCD panels. The input voltage range of the circuit is from 7.5V to 24V. The maximum RMS lamp current is set to 6mA and the maximum RMS striking voltage is set to 1800V. Table 1 lists some important components and Table 2 lists the component suppliers' contact information. soidal waveforms over the entire input range to improve CCFL lifetime. The lamp brightness is adjusted by turning the lamp on and off with a DPWM signal. The DPWM frequency can be accurately adjusted with a resistor. The brightness of the lamp is proportional to the duty cycle of the DPWM signal, which is controlled either with a 2-wire SMBus-compatible interface, with an external ALS, or with an external PWM signal. The device also includes safety features that effectively protect against single-point fault conditions such as lampout and secondary short-circuit faults. An internal 5.35V linear regulator powers the MOSFET drivers and most of the internal circuitry. Figure 2 is the functional diagram of the MAX8759 and Figure 3 is the detailed diagram of the SMBus and ALS input block.
MAX8759
Detailed Description
The MAX8759 controls a full-bridge resonant inverter to convert an unregulated DC input into a high-frequency AC output for powering CCFLs. The resonant operation maximizes striking capability and provides near-sinu-
Resonant Operation
Table 1. List of Important Components
DESIGNATION DESCRIPTION 10F 20%, 25V X5R ceramic capacitor (1210) Murata GRM32DR61E106M TDK C3225X5R1E106M 2.2F 10%, 25V X5R ceramic capacitors (0805) Murata GRM21BR61E225K TDK C2012X5R1E225K 10pF 10%, 3kV HV ceramic capacitor (1808) Kemet C1808C100KHGAC TDK C4520C0G3F100F Dual n-channel MOSFETs, 30V, 0.095, 6-pin SOT23 Fairchild FDC6561AN CCFL transformer, 1:110 turns ratio TMP UI9.8L type
C1
C2, C3
C4
NH1/2, NL1/2
T1
Table 2. Component Suppliers
SUPPLIER Fairchild Semiconductor Kemet Murata TDK TMP WEBSITE www.fairchildsemi.com www.kemet.com www.murata.com www.components.tdk.com www.tmp.com
The MAX8759 drives four n-channel power MOSFETs that make up the zero-voltage-switching (ZVS) fullbridge inverter as shown in Figure 4. Assume that NH1 and NL2 are on at the beginning of a switching cycle as shown in Figure 4(a). The primary current flows through MOSFET NH1, DC blocking capacitor C2, the primary side of transformer T1, and MOSFET NL2. During this interval, the primary current ramps up until the controller turns off NH1. When NH1 is turned off, the primary current forward biases the body diode of NL1, which clamps the LX1 voltage just below ground as shown in Figure 4(b). When the controller turns on NL1, its drain-to-source voltage is near zero because its forward-biased body diode clamps the drain. Since NL2 is still on, the primary current flows through NL1, C2, the primary side of T1, and NL2. Once the primary current drops to the minimum current threshold (6mV/R DS(ON) ), the controller turns off NL2. The remaining energy in T1 charges up the LX2 node until the body diode of NH2 is forward biased. When NH2 turns on, it does so with near-zero drain-to-source voltage. The primary current reverses polarity as shown in Figure 4(c), beginning a new cycle with the current flowing in the opposite direction, with NH2 and NL1 on. The primary current ramps up until the controller turns off NH2. When NH2 is turned off, the primary current forward biases the body diode of NL2, which clamps the LX2 voltage just below ground as shown in Figure 4(d). After the LX2 node goes low, the controller losslessly turns on NL2. Once the primary current drops to the minimum current threshold, the controller turns off NL1. The remaining energy charges up the LX1 node until the body diode of NH1 is forward biased. Finally, NH1 losslessly turns on, beginning a new cycle as shown in Figure 4(a). Note that switching transitions on all four power MOSFETs occur under ZVS conditions, which reduces transient power losses and EMI.
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
BATT GND VCC RDY VALS ISEC 1.21V
LINEAR REGULATOR
BIAS EN 4.3V RDY UVLO COMPARATOR VCC
MAX8759
OC COMP OC ZX S Q R OPEN-LAMP COMP 135A FAULT LATCH 1A 4V 230mV VFB FW MAX VREF ERROR AMP BST1 1000A OC 100A DH GH1 LX1 BST2 2.3V OV COMP DWPM OSC 8-BIT COUNTER DPWM LATCH S Q ALS ADC 40k PWM ADC ILIM COMP BRIGHTNESS CONTROL R DPWM COMP ZERO-CROSS ZX DETECTIONS AND DELAY BLOCK LX_ DL GL2 PGND1 MUX 400mV DEL PWM COMP MIN TON GATE-DRIVER CONTROL STATE MACHINE DH GH2 LX2 VDD DL GL1 PGND2 BATT UV COMP S R Q SHUTDOWN TFLT
MIN 600mV IFB1 IFB2 FW
COMP
VFB
FREQ SCL
SMBus SDA ALS PWMI
Q R TON FF S Q
PWMO
Figure 2. MAX8759 Functional Diagram 14 ______________________________________________________________________________________
Low-Cost, SMBus, CCFL Backlight Controller MAX8759
PWMO
BUFFER PWMI A D "1" PWM_MD BUFFER ALS DIGITAL POT A OFFSET ALS CLAMP PWM_SEL MUX DIGITAL MULTIPLIER MUX DPWM SETTING
MUX
D
ALS_CTL FAULT/ STATUS REGISTER 0X02 ALS STATUS REGISTER 0X04 ALS LOW-LIMIT REGISTER 0X05 ALS HIGH-LIMIT REGISTER 0X06 BRIGHT CONTROL REGISTER 0X00 DEVICE CONTROL REGISTER 0X01 INVERTER ON/OFF
SDA SCL
SMBus AND AMBIENT-LIGHT-SENSOR INPUT BLOCK SMBus INTERFACE
Figure 3. MAX8759 SMBus and Ambient-Light-Sensor Input Block
A simplified CCFL inverter circuit is shown in Figure 5 (a). The full-bridge power stage is simplified and represented as a square-wave AC source. The resonant tank circuit can be further simplified to Figure 5(b) by removing the transformer. C S is the primary series capacitor, CS' is the series capacitance reflected to the secondary, CP is the secondary parallel capacitor, N is the transformer turns ratio, L is the transformer secondary leakage inductance, and R L is an idealized resistance that models the CCFL in normal operation.
Figure 6 shows the frequency response of the resonant tank's voltage gain under different load conditions. The primary series capacitor is 1F, the secondary parallel capacitor is 15pF, the transformer turns ratio is 1:93, and the secondary leakage inductance is 260mH. Notice that there are two peaks, fS, and fP, in the frequency response. The first peak fS is the series resonant peak determined by the secondary leakage inductance (L) and the series capacitor reflected to the secondary (C'S): fS = 1 2 LCS
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
VBATT VBATT
NH1 ON T1 C2 LX1 LX2
NH2 OFF
NH1 OFF T1 C2 LX1 LX2
NH2 ON
NL1 OFF
NL2 ON
NL1 ON
NL2 OFF
(a) VBATT
(c) VBATT
NH1 OFF T1 C2 LX1 LX2
NH2 OFF
NH1 OFF T1 C2 LX1 LX2
NH2 OFF
NL1 ON
NL2 ON
NL1 ON
NL2 ON
(BODY DIODE TURNS ON FIRST) (b) (d)
(BODY DIODE TURNS ON FIRST)
Figure 4. Resonant Operation
The second peak fP is the parallel resonant peak determined by the secondary leakage inductance (L), the parallel capacitor (CP), and the series capacitor reflected to the secondary (C'S): fP = 2 L 1 CSCP CS + CP
The inverter is designed to operate between these two resonant peaks. When the lamp is off, the operating point of the resonant tank is close to the parallel resonant peak due to the lamp's infinite impedance. The circuit displays the characteristics of a parallel-loaded
16
resonant converter. While in parallel-loaded resonant operation, the inverter behaves like a voltage source to generate the necessary striking voltage. Theoretically, the output voltage of the resonant converter increases until the lamp is ionized or until it reaches the IC's secondary voltage limit. Once the lamp is ionized, the equivalent load resistance decreases rapidly and the operating point moves toward the series resonant peak. While in series resonant operation, the inverter behaves like a current source.
Lamp-Current Regulation
The MAX8759 uses a lamp-current control loop to regulate the current delivered to the CCFL. The heart of the control loop is a transconductance error amplifier. The
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
CS
1:N
L
AC SOURCE
4 CP CCFL 3 RL INCREASING 2
(a)
C'S =
CS N2 L
VOLTAGE GAIN (V/V) CP RL
1
AC SOURCE
0 0 20 40 60 80 100 FREQUENCY (kHz)
(b)
Figure 5. Equivalent Resonant Tank Circuit
Figure 6. Frequency Response of the Resonant Tank
AC lamp current is sensed with a resistor connected in series with the low-voltage terminal of the lamp. The MAX8759 has two lamp-current feedback inputs (IFB1 and IFB2) to support dual-lamp application. The voltages across the sense resistors are fed to the IFB1 and IFB2 inputs and are internally full-wave rectified. The transconductance error amplifier selects the higher one of the two feedback signals and compares the rectified voltage with an internal threshold to generate an error current. The error current charges and discharges a capacitor connected between COMP and ground to create an error voltage (VCOMP). VCOMP is then compared with an internal ramp signal to set the high-side MOSFET switch on-time (tON).
Feed-forward control is implemented by increasing the internal voltage ramp rate for higher VBATT. This has the effect of varying tON as a function of the input voltage while maintaining approximately the same signal levels at VCOMP. Since the required voltage change across the compensation capacitor is minimal, the controller's response to input voltage changes is essentially instantaneous.
Lamp Startup
A CCFL is a gas-discharge lamp that is normally driven in the avalanche mode. To start ionization in a nonionized lamp, the applied voltage (striking voltage) must be increased to the level required for the start of avalanche. At low temperatures, the striking voltage can be several times the typical operating voltage. Because of the MAX8759's resonant topology, the striking voltage is guaranteed. Before the lamp is ionized, the lamp impedance is infinite. The transformer secondary leakage inductance and the high-voltage parallel capacitor determine the unloaded resonant frequency. Since the unloaded resonant circuit has a high Q, it can generate very high voltage across the lamp.
Feed-Forward Control
The MAX8759 is designed to maintain tight control of the lamp current under all transient conditions. The feed-forward control instantaneously adjusts the ontime for changes in input voltage (VBATT). This feature provides immunity to input-voltage variations and simplifies loop compensation over wide input-voltage ranges. The feed-forward control also improves the line regulation for short DPWM on-times and makes startup transients less dependent on the input voltage.
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
Dimming Control
The MAX8759 controls the brightness of the CCFL by "chopping" the lamp current on and off using a low-frequency (between 100Hz and 350Hz) DPWM signal. The frequency of the internal DPWM oscillator is adjustable through a resistor connected between the FREQ pin and GND. The CCFL brightness is proportional to the DPWM duty cycle, which can be adjusted from 10.15% to 100%. In DPWM operation, the COMP voltage controls the dynamics of the lamp-current envelope. At the beginning of the DPWM ON cycle, the average value of the lamp-current feedback signal is below the regulation point, so the transconductance error amplifier sources current into the COMP capacitor. The switch on-time (tON) gradually increases as VCOMP rises, which provides soft-start. At the end of the DPWM ON cycle, the MAX8759 turns on a 110A internal current source. The current source linearly discharges the COMP capacitor, gradually decreasing tON, and providing soft-stop. The DPWM frequency can be set with an external resistor. Connect a resistor between FREQ and GND. The DPWM frequency is given by the following equation: fDPWM = 210Hz x 169k / RFREQ The adjustable range of the DPWM frequency is between 100Hz and 350Hz (RFREQ is between 100k and 350k). The MAX8759 has three ways for brightness control. The brightness can be controlled by a 2-wire serial interface (SMBus), by an external PWM signal, or by an external ambient-light sensor signal. There are five operating modes, which can be selected by setting bits 1 to 3 in device control register 0x01 (see the SMBus Register Definitions section for details). ALS Mode The MAX8759 can work with several types of ambientlight sensors. The ideal ambient-light sensors should have a linear response to ambient light and should have a spectral response equivalent to that of the human eye. Ambient-light sensors must provide filtering of low-frequency harmonics found in the electrical spectrum of the many light sources. The ALS's output should be a DC analog voltage that is linearly proportional to the ambient luminance. In ALS mode, the MAX8759 sets the brightness based on the analog voltage on the ALS pin. The ALS pin is connected to the output of an external ambient-light sensor. The usable input-voltage range of the ALS pin is 0 to 1.8V. The MAX8759 compares the ALS input voltage against user-programmable low and high limits. When the ALS input voltage is below the low limit, the brightness is clamped to the ALS low limit. When the ALS input voltage is above the high limit, the brightness is clamped to the ALS high limit. If the minimum ALS setting is below 10%, the brightness is clamped to 10%. Figure 7 shows the brightness change as a function of the ALS voltage. The ALS input voltage is sampled every DPWM period and is loaded in ALS status register 0x04. The analog voltage on the ALS pin is converted into an 8-bit digital code. The total number of brightness levels is 256. One step change results in a 0.391% change in the DPWM duty cycle. PWM Mode In PWM mode, the MAX8759 sets the brightness based on the duty cycle of the PWMI signal. The absolute minimum brightness is 10%. If the PWMI duty cycle is less than 10%, the brightness stays at 10%. The frequency range of the PWMI signal is between 5kHz and 50kHz when the PWMO capacitor is 1F. SMBus Mode In SMBus mode, the MAX8759 sets the brightness based on the brightness control register (0x00). The brightness control register contains 8 bits and supports 256 brightness levels. A setting of 0xFF for register 0x00 sets the inverter to the maximum brightness. A setting of 0x00 for register 0x00 sets the inverter to the minimum brightness (10%). ALS with DPST Mode In ALS with DPST mode, the MAX8759 sets the brightness based on the analog voltage on the ALS pin and duty cycle at the PWMI pin. The MAX8759 lowers the ALS brightness setting by an additional amount that is proportional to the duty cycle of the PWMI signal. For example, if the ALS brightness setting is 80% and the duty cycle of PWMI signal is 60%, the resulting brightness setting is 80% x 60% = 48%.
SMBus with DPST Mode
In SMBus with DPST mode, the MAX8759 sets the brightness based on the brightness control register (0x00). The MAX8759 lowers the SMBus brightness setting by an additional amount that is proportional to the duty cycle of the PWMI signal. For example, if the brightness control register is set to 0x80 (corresponding to 50% brightness setting) and the duty cycle of the PWMI signal is 60%, the resulting brightness setting is 50% x 60% = 30%.
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Low-Cost, SMBus, CCFL Backlight Controller
Fault Protections
Lamp-Out Protection For safety, the MAX8759 monitors the lamp-current feedback inputs (IFB1 and IFB2) to detect faulty or open CCFL tubes. As described in the Lamp-Current Regulation section, the voltage on IFB1 and IFB2 is internally full-wave rectified. If the rectified IFB1 or IFB2 voltage is below 600mV, the MAX8759 charges the TFLT capacitor with 1A. The MAX8759 sets the fault latch and the device is shut down when the voltage on TFLT exceeds 4V. Unlike the normal shutdown mode, the linear regulator output (V CC ) remains at 5.35V. Clearing bit 0 of the device control register (0x01) or cycling the input power clears the fault latch. During the fault-delay period, the current control loop tries to maintain the lamp-current regulation by increasing the high-side MOSFET on-time. Because the lamp impedance is very high when it is open, the transformer secondary voltage rises as a result of the high Q-factor of the resonant tank. Once the secondary voltage exceeds the overvoltage threshold, the MAX8759 turns on a 1000A current source that discharges the COMP capacitor. The on-time of the high-side MOSFET is reduced, lowering the secondary voltage as the COMP voltage decreases. Therefore, the peak voltage of the transformer secondary winding never exceeds the limit during the lamp-out delay period. Primary Overcurrent Protection The MAX8759 senses primary current in each switching cycle. When the regulator turns on the low-side MOSFET, a comparator monitors the voltage drop from LX_ to PGND_. If the voltage exceeds the current-limit threshold (430mV, typ), the regulator immediately turns off the high-side switch to prevent the transformer primary current from increasing further.
1.0
Secondary Voltage Limiting (VFB) The MAX8759 reduces the voltage stress on the transformer's secondary winding by limiting the secondary voltage during startup and open-lamp faults. The AC voltage across the transformer secondary winding is sensed through a capacitive voltage-divider formed by C4 and C5 in Figure 1. The voltage across C5 is fed to the VFB input. An overvoltage comparator compares the VFB peak voltage with a 2.3V (typ) internal threshold. Once the VFB peak voltage exceeds the overvoltage threshold, the MAX8759 turns on an internal 1000A current source that discharges the COMP capacitor. The high-side MOSFET's on-time shortens as the COMP voltage decreases, limiting the transformer secondary's peak voltage at the threshold determined by the capacitive voltage-divider. Secondary Undervoltage Protection (VFB) The MAX8759 senses the VFB voltage for undervoltage condition. During the DPWM ON period, if the VFB voltage is below the undervoltage threshold (230mV, typ) continuously for an internal delay period (250s typ, for RFREQ = 169k), the MAX8759 shuts down. Secondary Current Limit (ISEC) The secondary current limit provides fail-safe current limiting in case of a short circuit or leakage from the lamp high-voltage terminal to ground that prevents the current control loop from functioning properly. ISEC monitors the voltage across a sense network placed between the transformer's low-voltage secondary terminal and ground. The ISEC voltage is continuously compared to the ISEC regulation threshold (1.21V, typ). Any time the ISEC voltage exceeds the threshold, the MAX8759 turns on a 1000A current source that discharges the COMP capacitor, reducing the on-time of the high-side switches. At the same time, the MAX8759 charges the TFLT capacitor with a 135A current. The MAX8759 sets the fault latch and shuts down when the voltage on TFLT exceeds 4V. Clearing bit 0 of the device control register (0x01) or cycling the input power clears the fault latch.
MAX8759
NORMALIZED BRIGHTNESS
0.8
0.6
Linear Regulator Output (VCC)
The internal linear regulator steps down the DC input voltage at BATT pin to 5.35V (typ). The linear regulator supplies power to the internal control circuitry of the MAX8759 and is also used to power the MOSFET drivers by connecting VCC to VDD. The VCC voltage drops to 4.5V in shutdown.
0 0.4 0.8 1.2 1.6 2.0
0.4
0.2
0 VALS (V)
POR and UVLO
The MAX8759 includes power-on reset (POR) and undervoltage lockout (UVLO) features. POR resets the fault latch and sets all the SMBus registers to their POR
19
Figure 7. Normalized Brightness vs. ALS Voltage
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
WRITE-BYTE FORMAT S ADDRESS 7 BITS
SLAVE ADDRESS
WR 1b
ACK 1b
COMMAND 8 BITS
COMMAND BYTE: SELECTS WHICH REGISTER YOU ARE WRITING TO
ACK 1b
DATA 8 BITS
ACK 1b
P
--
--
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE
READ-BYTE FORMAT S ADDRESS 7 BITS
SLAVE ADDRESS
WR 1b
ACK 1b
COMMAND 8 BITS
ACK 1b
S
ADDRESS 7 BITS
RD 1b
ACK 1b
DATA 8 BITS
/// 1b
P
--
--
--
COMMAND BYTE: SELECTS WHICH REGISTER YOU ARE READING FROM
SLAVE ADDRESS: REPEATED DATA BYTE: READS FROM THE DUE TO CHANGE IN DATAREGISTER SET BY THE COMMAND FLOW DIRECTION BYTE
SEND-BYTE FORMAT S ADDRESS 7 BITS WR 1b ACK 1b COMMAND 8 BITS ACK 1b P
RECEIVE-BYTE FORMAT S ADDRESS 7 BITS
SLAVE ADDRESS
RD 1b
ACK 1b
DATA 8 BITS
/// 1b
P
--
--
--
--
COMMAND BYTE: SENDS COMMAND WITH NO DATA; USUALLY USED FOR ONE-SHOT COMMAND
DATA BYTE: READS DATA FROM THE REGISTER COMMANDED BY THE LAST READ-BYTE OR WRITE-BYTE TRANSMISSION; ALSO USED FOR SMBus ALERT RESPONSE RETURN ADDRESS
S = START CONDITION P = STOP CONDITION
SHADED = SLAVE TRANSMISSION ACK = ACKNOWLEDGED = 0
WR = WRITE = 0 RD = READ = 1 /// = NOT ACKNOWLEDGED = 1
Figure 8. SMBus Protocols
values. POR occurs when VCC rises above 1.75V (typ). The UVLO occurs when VCC is below 4.2V (typ). The MAX8759 disables both high-side and low-side switch drivers below the UVLO threshold.
SMBus Interface (SDA, SCL)
The MAX8759 supports an SMBus-compatible 2-wire digital interface. SDA is the bidirectional data line and SCL is the clock line of the 2-wire interface corresponding respectively to SMBDATA and SMBCLK lines of the SMBus. SDA and SCL have Schmidt-triggered inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. The MAX8759 uses the write-byte and read-byte protocols (Figure 8). The SMBus protocols are documented in System Management Bus Specification V1.08 and are available at http://www.sbs-forum.org/. The MAX8759 is a slave-only device and responds to the 7-bit address 0b0101100. The read and write commands can be distinguished by adding ONE more bit (R/W bit) to the end of the 7-bit slave address, with one indicating read and zero indicating write. The MAX8759 has seven registers: a brightness control register (0x00), a device control register (0x01), a fault/status register (0x02), an identification register (0x03), an ALS status register (0x04), an ALS low-limit register (0x05),
Low-Power Shutdown
The MAX8759 is placed into shutdown by clearing bit 0 of the device control register (0x01).When the MAX8759 is shut down, all functions of the IC are turned off except the 5.35V linear regulator. In shutdown, the linear regulator output voltage drops to 4.5V and the supply current is 6A (typ). While in shutdown, the fault latch is reset. The device can be reenabled by setting bit 0 of the device control register to 1.
Ambient-Light-Sensor Supply Pin (VALS)
The MAX8759 provides the supply voltage of the ALS through the VALS pin. VALS is internally connected to the 5.35V linear regulator output through a p-channel MOSFET. The p-channel MOSFET is turned on when the MAX8759 is enabled and turned off when the part is disabled. Bypass VALS to ground with a minimum 0.lF ceramic capacitor. Place the capacitor as close to the ALS supply input as possible.
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
A
tLOW
B
tHIGH
C
D
E
F
G
H
I
J
K
L
M
SMBCLK
SMBDATA
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tHD:DAT
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER. K = ACKNOWLEDGE CLOCK PULSE. L = STOP CONDITION, DATA EXECUTED BY SLAVE. M = NEW START CONDITION .
A = START CONDITION. B = MSB OF ADDRESS CLOCKED INTO SLAVE. C = LSB OF ADDRESS CLOCKED INTO SLAVE. D = R/W BIT CLOCKED INTO SLAVE. E = SLAVE PULLS SMBDATA LINE LOW .
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER. G = MSB OF DATA CLOCKED INTO SLAVE. H = LSB OF DATA CLOCKED INTO SLAVE. I = SLAVE PULLS SMBDATA LINE LOW.
Figure 9. SMBus Write Timing
and an ALS high-limit register (0x06). The MAX8759 only acknowledges these seven registers. Communication starts with the master signaling the beginning of a transmission with a START condition, which is a high-to-low transition on SDA while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition, which is a low-to-high transition on SDA while SCL is high. The bus is then free for another transmission. Figures 9 and 10 show the timing diagrams for signals on the 2-wire interface. The address byte, command byte, and data byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the MAX8759 since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. If the MAX8759 receives its correct slave
address followed by R/W = 0, it expects to receive 1 or 2 bytes of information (depending on the protocol). If the device detects a START or STOP condition prior to clocking in the bytes of data, it considers this an error condition and disregards all the data. If the transmission is completed correctly, the registers are updated immediately after a STOP (or RESTART) condition. If the MAX8759 receives its correct slave address followed by R/W = 1, it expects to clock out the register data selected by the previous command byte.
SMBus Register Definitions
All MAX8759 registers are byte wide and accessible through the read/write byte protocols mentioned in the previous section. Their bit assignments are provided in the following sections with reserved bits containing a default value of zero. Table 3 summarizes the register assignments, as well as each register's POR state. During shutdown, the serial interface remains fully functional.
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
A tLOW
B tHIGH
C
D
E
F
G
H
I
J
K
SMBCLK
SMBDATA
tSU:STA tHD:STA A = START CONDITION. B = MSB OF ADDRESS CLOCKED INTO SLAVE. C = LSB OF ADDRESS CLOCKED INTO SLAVE. D = R/W BIT CLOCKED INTO SLAVE.
tSU:DAT
tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW. F = ACKNOWLEDGE BIT CLOCKED INTO MASTER. G = MSB OF DATA CLOCKED INTO MASTER. H = LSB OF DATA CLOCKED INTO MASTER.
tSU:DAT
tSU:STO
tBUF
I = ACKNOWLEDGE CLOCK PULSE. J = STOP CONDITION. K = NEW START CONDITION.
Figure 10. SMBus Read Timing
Table 3. Commands Description
DATA-REGISTER BIT ASSIGNMENT SMBus COMMAND POR PROTOCOL BYTE STATE Read and Write Read and Write Read Only Read Only Read Only Read and Write Read and Write BIT 7 (MSB) BR7 BIT 6 BRT6 BIT 5 BRT5 BIT 4 BR4 BIT 3 BRT3 ALS_CTL BIT 2 BRT2 BIT 1 BRT1 BIT 0 (LSB) BRT0
0x00 0x01 0x02 0x03 0x04 0x05 0x06
0xFF 0x00 N/A 0x01 0x00 0x00 0xFF
Reserved Reserved Reserved Reserved MFG4 ALS7 ALSLL7 ALSHL7 MFG3 ALS6 ALSLL6 ALSHL6
ALSDEL1 ALSDEL0
PWM_MD PWM_SEL LAMP_CTL FAULT REV0 ALS0 ALSLL0 ALSHL0
Reserved Reserved LAMP_STAT OV_CURR Reserved MFG2 ALS5 ALSLL5 ALSHL5 MFG1 ALS4 ALSLL4 ALSHL4 MFG0 ALS3 ALSLL3 ALSHL3 REV2 ALS2 ALSLL2 ALSHL2 REV1 ALS1 ALSLL1 ALSHL1
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Low-Cost, SMBus, CCFL Backlight Controller
Brightness Control Register [0x00] (POR = 0xFF) The brightness control register of the MAX8759 contains 8 bits and supports 256 brightness levels. A writebyte cycle to register 0x00 sets the brightness level if the inverter is in SMBus mode. A write-byte cycle to register 0x00 has no effect if the inverter is not in
BIT 7 (R/W) BRT7 BIT 6 (R/W) BRT6 BIT 5 (R/W) BRT5 BIT 4 (R/W) BRT4
SMBus mode. A read-byte cycle to register 0x00 returns the current brightness level regardless of the operation mode. A setting of 0xFF for register 0x00 sets the inverter to the maximum brightness. A setting of 0x00 for register 0x00 sets the inverter to the minimum brightness.
MAX8759
BIT 3 (R/W) BRT3
BIT 2 (R/W) BRT2
BIT 1 (R/W) BRT1
BIT 0 (R/W) BRT0
BRT[7..0]: 256 brightness levels.
Device Control Register [0x01] (POR = 0x00) This register has a single bit that controls the inverter ON/OFF state, 3 bits that control the operating mode of
the inverter, and 2 bits for setting ALS delay time. The remaining bits are reserved for future use.
BIT 7 Reserved
BIT 6 Reserved
BIT 5 (R/W) ALSDEL1
BIT 4 (R/W) ALSDEL0
BIT 3 (R/W) ALS_CTL
BIT 2 (R/W) PWM_MD
BIT 1 (R/W) PWM_SEL
BIT 0 (R/W) LAMP_CTL
ALSDEL1: ALS delay select bit. ALSDEL0: ALS delay select bit. ALS_CTL: Ambient-light-sensor select bit (1 = use ALS, 0 = not use ALS). PWM_MD: PWM mode select bit (1 = absolute brightness, 0 = percentage change). PWM_SEL: Brightness control select bit (1 = control by PWM, 0 = control by SMBus). LAMP_CTL: Inverter on/off bit (1 = on, 0 = off).
A value of 1 written to LAMP_CTL turns on the lamp as quickly as possible. A value of zero written to LAMP_CTL immediately turns off the lamp. The PWM_SEL bit determines whether the SMBus or PWM input should control brightness when the inverter is not in ALS mode. This bit has no effect when ALS_CTL is set to 1. The PWM_MD bit selects the manner in which the PWM input is to be interpreted. When this bit is zero, the PWM input reflects a percentage change in the current brightness (i.e., DPST mode) and follows the following equation: DPST brightness = BRTCURRENT x DPWM
where BRTCURRENT is the current brightness setting from either ALS or SMBus without influence from the PWM input and DPWM is the duty cycle of the PWM signal. When PWM_MD bit is 1, the PWM input has no effect on the brightness setting unless the inverter is in PWM mode. When ALS_CTL is 1, the inverter controls brightness based primarily on the light reading from the ALS. However, the ALS brightness setting can be modified if the PWM_MD bit is set to zero. When the ALS_CTL bit is zero, the inverter controls the brightness according to the PWM input (PWM mode), the SMBus setting (SMBus mode), or a combination of the two (SMBus mode with DPST).
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Low-Cost, SMBus, CCFL Backlight Controller
The relationships among these 3 control bits can be thought of as specifying an operating mode for the inverter. The defined modes are shown in Table 4. Note that depending on the settings of some bits, other bits have no effect and are don't-care bits--they are shown with a value of X in Table 4. For example, when the ALS_CTL bit is 1, the value of PWM_SEL has no effect on the operation of the inverter, so its value is shown as X. ALSDEL0 and ALSDEL1 set the delay time required to change the brightness in ALS mode. This delay time is necessary for smooth transitions during brightness change. Table 5 shows the available delays. Note that the behavior of register 0x00 (brightness control register) is affected by certain combinations of the control bits as shown in Table 4. When SMBus mode is selected, register 0x00 reflects the last value written to it. However, when any non-SMBus mode is selected, register 0x00 reflects the current brightness value based on the current mode of operation.
MAX8759
Table 4. Operating Modes Selected by Device Control Register Bits 3, 2, and 1
ALS_CTL 1 1 0 0 0 PWM_MD 1 0 X 1 0 PWM_SEL X X 1 0 0 MODE ALS mode ALS mode with DPST PWM mode SMBus mode SMBus mode with DPST
Table 5. Delay Time Selected by Device Control Register Bits 5, 4
ALSDEL1 1 1 0 0 ALSDEL0 1 0 1 0 DELAY TIME (ms) 25 15 10 20 (default) N PERIODS 5 3 2 4
Fault/Status Register [0x02] (POR = 0x00)
This register has 3 status bits that allow monitoring the inverter's operating state. Bit 0 is a logical OR of openlamp fault and overcurrent fault. Bit 2 indicates secondary/UL overcurrent fault. Bit 3 always indicates the current lamp on/off status. The value of this bit is one whenever both lamp 1 and lamp 2 are on. The value of this bit is zero whenever lamp 1 or lamp 2 is off. The
BIT 7 (R) Reserved BIT 6 (R) Reserved BIT 5 (R) Reserved BIT 4 (R) Reserved
remaining bits are reserved for future use. All reserved bits return a zero when read. All the bits in this register are read only. A write-byte cycle to register 0x02 has no effect. Write zero to bit 0 of register 0x01 to clear the fault bit.
BIT 3 (R) LAMP_STAT
BIT 2 (R) OV_CURR
BIT 1 (R) Reserved
BIT 0 (R) FAULT
LAMP_STAT: Lamp status bit (1 = lamp 1 and lamp 2 are on, 0 = lamp 1 or lamp 2 is off). OV_CURR: Secondary/UL overcurrent fault (1 = secondary/UL overcurrent fault, 0 = no secondary/UL overcurrent). FAULT: Fault bit (1 = open-lamp or primary overcurrent fault, 0 = no fault).
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Low-Cost, SMBus, CCFL Backlight Controller
Identification Register [0x03] (POR = 0x01) The identification register contains two bit fields to denote the manufacturer and the silicon revision. The bit field widths allow up to 32 vendors with up to eight silicon revisions each. This register is read only. A writebyte cycle to register 0x03 has no effect.
MAX8759
BIT 7 (R) MFG4
BIT 6 (R) MFG3
BIT 5 (R) MFG2
BIT 4 (R) MFG1
BIT 3 (R) MFG0
BIT 2 (R) REV2
BIT 1 (R) REV1
BIT 0 (R) REV0
MFG[4..0]: Manufacturer ID (the vendor ID for Maxim is 0). REV[2..0]: Silicon rev (revs 0-7 allowed for silicon revisions).
ALS Status Register [0x04] (POR = 0x00) The ALS should return a value reflecting the brightness setting based on the ALS input. The register has 8 bits that define a full range of 256 brightness levels. The
register is read only and a write-byte cycle has no effect. A read-byte cycle to register 0x04 returns the current reading of ALS, regardless of the operating mode set in register 0x01.
BIT 7 (R) ALS7
BIT 6 (R) ALS6
BIT 5 (R) ALS5
BIT 4 (R) ALS4
BIT 3 (R) ALS3
BIT 2 (R) ALS2
BIT 1 (R) ALS1
BIT 0 (R) ALS0
ALS[7..0]: 256 steps of ambient-light sensor reading.
ALS Low-Limit Register [0x05] (POR = 0x00) The value in this read-write register reflects the lowest possible brightness value the inverter can set based on inputs from the ALS. Users can change this value so that they can control the effect of ALS. A write-byte cycle to register 0x05 sets the lowest possible brightness value
BIT 7 (R/W) ALSLL7 BIT 6 (R/W) ALSLL6 BIT 5 (R/W) ALSLL5 BIT 4 (R/W) ALSLL4
that can be set based on ALS inputs. If the brightness setting due to ALS is lower than the value written to this register, the inverter immediately increases the brightness setting to the newly written value. A read-byte cycle to register 0x05 returns the current minimum brightness value that can be set based on ALS inputs.
BIT 3 (R/W) ALSLL3 BIT 2 (R/W) ALSLL2 BIT 1 (R/W) ALSLL1 BIT 0 (R/W) ALSLL0
ALSLL[7..0]: The lowest brightness setting that can be set based on ALS inputs.
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25
Low-Cost, SMBus, CCFL Backlight Controller MAX8759
ALS High-Limit Register [0x06] (POR = 0xFF) The value in this read-write register reflects the highest possible brightness value the inverter can set based on inputs from the ALS. Users can change this value so that they can control the effect of ALS. A write-byte cycle to register 0x06 sets the highest possible brightness value that can be set based on ALS inputs. If the
BIT 7 (R/W) ALSHL7 BIT 6 (R/W) ALSHL6 BIT 5 (R/W) ALSHL5 BIT 4 (R/W) ALSHL4
brightness setting due to ALS is higher than the value written to this register, the inverter immediately decreases the brightness setting to the newly written value. A read-byte cycle to register 0x06 returns the current maximum brightness value that can be set based on ALS inputs. The default value of register 0x06 is 0xFF, which corresponds to the maximum brightness.
BIT 3 (R/W) ALSHL3 BIT 2 (R/W) ALSHL2 BIT 1 (R/W) ALSHL1 BIT 0 (R/W) ALSHL0
ALSHL[7..0]: The highest brightness setting that can be set based on ALS inputs.
Applications Information
MOSFETs
The MAX8759 requires four external n-channel power MOSFETs: NL1, NL2, NH1, and NH2 to form a fullbridge inverter circuit. The controller senses the on-state drain-to-source voltage of the two low-side MOSFETs NL1 and NL2 to detect the transformer primary current, so the RDS(ON) of NL1 and NL2 should be matched. For instance, if dual MOSFETs are used to form the full bridge, NL1 and NL2 should be in one package. Since the MAX8759 uses the low-side MOSFET RDS(ON) for primary overcurrent protection, the lower the MOSFET R DS(ON) , the higher the current limit. Therefore, the user should select a dual logic-level n-channel MOSFET with low RDS(ON) to minimize conduction loss, and keep the primary current limit at a reasonable level. The regulator uses ZVS to softly turn on each of four switches in the full bridge. ZVS occurs when the external power MOSFETs are turned on when their respective drain-to-source voltages are near 0V (see the Resonant Operation section). ZVS effectively eliminates the instantaneous turn-on loss of MOSFETs caused by C OSS (drain-to-source capacitance) and parasitic capacitance discharge, and improves efficiency and reduces switching-related EMI.
minals of the lamps and ground. The voltages across the sense resistors are fed to IFB1 and IFB2 and are internally full-wave rectified. The MAX8759 controls the desired lamp current by regulating the average of the rectified IFB_ voltages. To set the RMS lamp current in a single-lamp application, determine the value of the sense resistor as follows: R1 = x 785mV 2 2 x ILAMP(RMS)
where ILAMP(RMS) is the desired RMS lamp current and 785mV is the typical value of the IFB1 regulation point specified in the Electrical Characteristics table. To set the RMS lamp current to 6mA, the value of the sense resistor should be 148. The closest standard 1% resistors are 147 and 150. The precise shape of the lamp-current waveform, which is dependent on lamp parasitics, influences the actual RMS lamp current. Use a true RMS current meter to make final adjustments.
Setting the Secondary Voltage Limit
The MAX8759 limits the transformer secondary voltage during startup and lamp-out faults. The secondary voltage is sensed through the capacitive voltage-divider formed by C4 and C5 (Figure 1). The VFB voltage is proportional to the CCFL voltage. The selection of the parallel resonant capacitor C1 is described in the Transformer Design and Resonant Component Selection section. C4 is usually between 10pF and 22pF. After the value of C4 is determined, select C5
Setting the Lamp Current
The MAX8759 senses the lamp current flowing through sense resistors connected between the low-voltage ter-
26
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Low-Cost, SMBus, CCFL Backlight Controller
using the following equation to set the desired maximum RMS secondary voltage VLAMP(RMS)_MAX: C5 = 2 x VLAMP(RMS)_ MAX 2.3V x C4 where VLAMP(RMS) is the maximum RMS lamp voltage in normal operation, and VIN(MIN) is the minimum DC input voltage. If the maximum RMS lamp voltage in normal operation is 700V and the minimum DC input voltage is 7.5V, the turns ratio should be greater than 104. The turns ratio of the transformer used in the circuit of Figure 1 is 110. The next step in the design procedure is to determine the desired operating frequency range. The MAX8759 is synchronized to the natural resonant frequency of the resonant tank. The resonant frequency changes with operating conditions, such as the input voltage, lamp impedance, etc. Therefore, the switching frequency varies over a certain range. To ensure reliable operation, the resonant frequency range must be within the operating frequency range specified by the CCFL transformer manufacturer. As discussed in the Resonant Operation section, the resonant frequency range is determined by transformer secondary leakage inductance L, the primary series DC blocking capacitors (CS), and the secondary parallel resonant capacitor CP. Since it is difficult to control the transformer leakage inductance, the resonant tank design should be based on the existing secondary leakage inductance of the selected CCFL transformer. The leakage inductance values can have large tolerance and significant variations among different batches. It is best to work directly with transformer vendors on leakage inductance requirements. The MAX8759 works best when the secondary leakage inductance is between 250mH and 350mH. Series capacitor CS sets the minimum operating frequency, which is approximately two times the series resonant peak frequency. Choose: CS N2 2 x f 2 MIN x L
MAX8759
where the 2.3V is the typical value of the VFB peak voltage when the lamp is open. To set the maximum RMS secondary voltage to 1800V when C4 is 10pF, use 10nF for C5.
Setting the Secondary Current Limit
The MAX8759 limits the secondary current even if the IFB_ sense resistors are shorted or transformer secondary current finds its way to ground without passing through the sense resistors. ISEC monitors the peak voltage across the sense network (R2 and C6 in Figure 1) connected between the low-voltage terminal of the transformer secondary winding and ground. Using an RCsense network instead of a single-sense resistor makes the secondary current-limit frequency dependent. The UL safety standard requires the AC peak current in a limitedcurrent circuit should not exceed 0.7mA for frequencies below 1kHz. For frequencies above 1kHz, the limit of 0.7mA is multiplied by the value of the frequency in kilohertz but should not exceed 70mA peak when the frequency is equal to or above 100kHz. To meet the UL current-limit specifications, determine the value of R2 using the current limit at 1kHz and determine the value of C6 using the current limit at 100kHz: R2 > 1.23V 0.7mA = 1.75k
70mA C6 < = 90nF 2 x 100kHz x 1.23V where 1.23V is the typical value of the ISEC peak voltage when the transformer secondary is shorted. The circuit of Figure 1 uses 3.9k for R2 and 68nF for C6.
Transformer Design and Resonant Component Selection
The transformer is the most important component of the resonant tank circuit. The first step in designing the transformer is to determine the transformer turns ratio. The ratio must be high enough to support the CCFL operating voltage at the minimum supply voltage. The transformer turns ratio N can be calculated as follows: VLAMP(RMS) N 0.9 x VIN(MIN)
where fMIN is the minimum operating frequency range. In the circuit of Figure 1, the transformer's turns ratio is 110 and its secondary leakage inductance is approximately 300mH. To set the minimum operating frequency to 30kHz, the total series capacitance needs to be less than 4.5F. Therefore, two 2.2F capacitors (C2 and C3) are used in Figure 1. Parallel capacitor CP sets the maximum operating frequency, which is also the parallel resonant peak frequency. Choose: CP CS 4 2 x f 2 MAX x L x CS - N2
In the circuit of Figure 1, to set the maximum operating frequency to 100kHz, CP needs to be larger than 8.6pF. A 10pF high-voltage capacitor (C4) is used in Figure 1.
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
The transformer core saturation should also be considered when selecting the operating frequency. The primary winding should have enough turns to prevent transformer saturation under all operating conditions. Use the following expression to calculate the minimum number of turns N1 of the primary winding: N1> DMAX x VIN(MAX) BS x S x fMIN C TFLT x 4 V 135A
TSEC _ SHORT =
Bootstrap Capacitors
The high-side gate drivers are powered using two bootstrap circuits. The MAX8759 integrates the bootstrap diodes so only two 0.1F bootstrap capacitors are needed. Connect the capacitors (C10 and C11 in Figure 1) between LX1 and BST1, and between LX2 and BST2 to complete the bootstrap circuits.
where DMAX is the maximum duty cycle (approximately 0.8) of the high-side switches, VIN(MAX) is the maximum DC input voltage, BS is the saturation flux density of the core, and S is the minimal cross-section area of the core.
Dual-Lamp Operating Circuit
The MAX8759 includes two lamp current feedback input pins that support dual-lamp applications with a minimum number of external components. Figure 11 shows the typical dual-lamp operating circuit.
COMP Capacitor Selection
The COMP capacitor sets the speed of the current loop that is used during startup, maintaining lamp-current regulation, and during transients caused by changing the input voltage. To maintain stable operation, the COMP capacitor (CCOMP) needs to be at least 3.3nF. The COMP capacitor also limits the dynamics of the lamp-current envelope in DPWM operation. At the end of the DPWM on cycle, the MAX8759 turns on a 110A internal current source to linearly discharge the COMP capacitor. Use the following equation to set the fall time: CCOMP = 110A x t FALL VCOMP
Layout Guidelines
Careful PC board layout is important to achieve stable operation. The high-voltage section and the switching section of the circuit require particular attention. The high-voltage sections of the layout need to be well separated from the control circuit. Most layouts for singlelamp notebook displays are constrained to long and narrow form factors, so this separation occurs naturally. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short and wide, especially at the ground terminals. This is essential for stable, jitter-free operation and high efficiency. 2) Use a star ground configuration for power and analog grounds. The power and analog grounds should be completely isolated--meeting only at the center of the star. The center should be placed at the analog ground pin (GND). Using separate copper islands for these grounds can simplify this task. Quiet analog ground is used for V CC , COMP, FREQ, and TFLT. 3) Route high-speed switching nodes away from sensitive analog areas (VCC, COMP, FREQ, and TFLT). Make all pin-strap control input connections to analog ground or VCC rather than power ground or VDD. 4) Mount the decoupling capacitor from VCC to GND as close as possible to the IC with dedicated traces that are not shared with other signal paths. 5) The current-sense paths for LX1 and LX2 to GND must be made using Kelvin-sense connections to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from outside, using the top copper layer, while connecting GND and LX inside (underneath) the 8-pin SO package.
where tFALL is the fall time of the lamp-current envelope and VCOMP is the COMP voltage when the lamp current is in regulation. At the beginning of the DPWM on cycle, the COMP capacitor is charged by a transconductance error amplifier. The rise time is about three times longer than the fall time.
Setting the Fault-Delay Time
The TFLT capacitor determines the delay time for both the open-lamp fault and secondary short-circuit fault. The MAX8759 charges the TFLT capacitor with a 1A current source during an open-lamp fault and charges the TFLT capacitor with a 135A current source during a secondary short-circuit fault. Therefore, the secondary short-circuit fault delay time is approximately 135 times shorter than that of open-lamp fault. The MAX8759 sets the fault latch when the TFLT voltage reaches 4V. Use the following equations to calculate the open-lamp fault delay (T OPEN _ LAMP ) and secondary short-circuit fault delay (TSEC_SHORT): TOPEN _ LAMP = C TFLT x 4 V 1A
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Low-Cost, SMBus, CCFL Backlight Controller MAX8759
INPUT VOLTAGE 7.5V TO 21V
F1 2A VCC 1 C7 0.1F BATT VDD 21 C8 1F GND BST2 DEL BST1 VCC C9 0.47F 28 VCC GH1 24 18 17 C10 0.1F C11 0.1F FDS6990A N1A N1B C1 22F 25V
27
11
C2 2.2F
SMB_DATA
2
MAX8759
SDA
LX1
16
T1 1:110
1 2 C4 10pF 3kV
HV LV
SMB_CLOCK
LX2 3 SCL GL1 7 PWMI PGND1 8 C12 1F
26
20
PWM INPUT
N2A
N2B
D3
19
FDS6990A R7 390k 1% C3 2.2F D4 C6 1nF R14 100k R1 150 1%
PWMO
PGND2 GL2
23 22
T2 1:110
GH2 9 R3 169k 1%
25
1 2
HV LV
FREQ
IFB1
12 C5 10pF 3kV R9 180k
IFB2
13
ISEC ALS SUPPLY C15 0.1F 5 VALS
15
R10 20k R12 180k VFB 14 10 R13 20k R8 390k 1% C17 1nF R15 100k
R2 150k 1%
ALS OUTPUT
6
ALS
COMP
TFLT
4 C14 0.22F
C13 6.8nF
Figure 11. Typical MAX8758 Dual-Lamp Operating Circuit
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29
Low-Cost, SMBus, CCFL Backlight Controller MAX8759
6) Ensure the feedback connections are short and direct. To the extent possible, IFB1, IFB2, VFB, and ISEC connections should be far away from the highvoltage traces and the transformer. 7) To the extent possible, high-voltage trace clearance on the transformer's secondary should be widely separated. The high-voltage traces should also be separated from adjacent ground planes to prevent lossy capacitive coupling. 8) The traces to the capacitive voltage-divider on the transformer's secondary need to be widely separated to prevent arcing. Moving these traces to opposite sides of the board can be beneficial in some cases.
Pin Configuration
BST1 ISEC GH1 GL1 VDD LX1
Chip Information
TRANSISTOR COUNT: 16,138 PROCESS: BiCMOS
TOP VIEW
21
GL2 PGND2 BST2 GH2 LX2 GND VCC
20
19
PGND1
18
17
16
15 14 13 12 11
VFB IFB2 IFB1 DEL COMP FREQ PWMO
22 23 24 25
MAX8759
26 27 28 1
BATT *EXPOSED PADDLE
10 9 8 6
ALS
2
SDA
3
SCL
4
TFLT
5
VALS
7
PWMI
TQFN 5mm x 5mm
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Low-Cost, SMBus, CCFL Backlight Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX8759
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1
2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
A A1 A3 b D E e k L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
DOWN BONDS ALLOWED
- 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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